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DTMF RECEIVER
DESCRIPTION
The SC9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state bus interface.
SC9270C/D
FEATURES
*Complete receiver in an 18-pin package *Excellent performance *CMOS, single 5 volt operation, *Widely operating voltage: 1.2V ~ 5.25V *Minimum board area *Central office quality *Low power consumption *Power-Down mode (SC9270D only) *Inhibit-mode (SC9270D only)
DIP-18
APPLICATIONS
*Paging systems *Repeater systems / Mobile radio *Credit card systems *Remote control *Personal computers
PIN CONFIGURATIONS
IN+ INGS VREF IC* IC* OSCI OSCO VSS
1 2 3 SC9270C 4 5 6 7 8 9
18 VDD 17 St/GT 16 ESt 15 StD 14 Q4 13 Q3 12 Q2 11 Q1 10 TOE
IN+ INGS VREF INH PWDN OSCI OSCO VSS
1 2 3 4 5 6 7 8 9 SC9270D
18 VDD 17 St/GT 16 ESt 15 StD 14 Q4 13 Q3 12 Q2 11 Q1 10 TOE
* Connect to VSS
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Rev: 1.1 2001.04.27
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BLOCK DIAGRAM
VDD VSS PWDN VREF INH
SC9270C/D
4
+
18
9
6
5
BIAS CIRCUIT
11 Q1
Chip ref Chip power IN+ 1 IN- 2 GS
+ -
Chip bias DIAL TONE FILTER
HIGH GROUP FILTER Zero crossing detectors
CODE DIGITAL CONVERTER DETECTION AND ALGORITHM LATCH
12 Q2 13 Q3 14 Q4
3
HIGH GROUP FILTER
Chip clock
St GT
STEERING LOGIC
7
OSCI
8
OSCO
17
St/GT
16
ESt
15
StD
10
TOE
Figure 1. block diagram
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3)
Characteristic
Power Supply Voltage Voltage on any pin Current at any pin Operating temperature Storage Temperature Package power dissipation
Symbol
VDD-VSS --Topr Tstg
Value
6 VSS-0.3 ~ VDD+0.3 10 -40~+85 -65~+150 500
Unit
V V mA C C mW
Note: 1. Absolute maximum ratings are those values beyond which damage to the device may occur. 2. Unless otherwise specified, all voltages are referenced to ground. 3. Power dissipation temperature derating: -12 mV / from 65C to 85C
RECOMMENDED OPERATING CONDITIONS (Note 1)
Parameter
Positive Supply Voltages Oscillator Clock Frequency Oscillator Frequency Tolerance
Symbol
VDD fc fc ---
Conditions
VSS=0V
Min
1.2 ---
Typ(Note 2)
5 3.579545 0.1
Max
----
Unit
V MHz %
Note: 1. Voltages are with respect to ground(Vss), unless otherwise stated. 2 .Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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DC ELECTRICAL CHARACTERISTICS
Parameter
SUPPLY
Operating Supply Voltage Operating Supply Current Power Consumption Standby Current VDD ICC PO IS VIL VIH IIH/IIL ISO RIN VTSt VOL VOH IOL IOH VREF ROR --f=3.579MHz; VDD=5V PWDN pin = VDD --VIN= VSS or VDD TOE(Pin 10)=0V @1kHz -No load No load VOUT=0.4V VOUT=4.6V No load --
SC9270C/D
Symbol Conditions Min
1.2 ----3.5 ------1.0 0.4 2.4 --
Typ
-3.0 15 ---0.1 7.5 10 2.35 0.03 4.97 2.5 0.8 -10
Max
5.25 7.0 35 100 1.5 --15 ------2.7 --
Unit
V mA mW A V V A A M V V A mA mA V k
INPUTS
Low Level Input Voltage High Level Input Voltage Input Leakage Current Pull up(Source) Current Input Impedance (IN+, IN-) Steering Threshold Voltage
OUTPUTS
Low Level Output Voltage High Level Output Voltage Output Low(Sink) Current Output High(Source) Current VREF Output Voltage VREF Output Resistance
OPERATING CHARACTERISTICS
Gain Setting Amplifier
Parameter
Input Leakage Current Input Resistance Input Offset Voltage Power Supply Rejection Common Mode Rejection DC Open Loop Voltage Gain Open Loop Unity Gain Bandwidth Output Voltage Swing Tolerable capacitive load(GS) Tolerable resistive load(GS) Common Mode Range
Symbol
IIN RIN VOS PSRR CMRR AVOL fC VO CL RL VCM
Conditions
VSS < VIN < VDD --1kHz -3.0V < VIN < 3.0V --RL100k to VSS --No load
Min
------------
Typ
100 10 25 60 60 65 1.5 4.5 100 50 3.0
Max
------------
Unit
nA M mV dB dB dB MHz VPP PF k VPP
Notes : 1. All voltages referenced to VDD unless otherwise noted. 2. VDD = 5.0V, VSS = 0V, TA = 25C .
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SC9270C/D
AC CHARACTERISTICS (All voltage referenced to Vss otherwise noted; VDD=5.0V, VSS=0V, TA=25C,
fCLK=3.579545 MHz, using test circuit of figure 2 & 3. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing)
Parameter
SIGNAL CONDITIONS
Symbo l
--
Test Conditions
Min
Typ
Max
Unit
Note:1,2,3,5,6,9,11 Note:1,2,3,5,6,9,11 Note:1,2,3,5,6,9,11 Note:1,2,3,5,6,9,11 Note:2,3,6,9,11 Note:2,3,6,9,11 Note:2,3,5,9,11 Note:2,3,5,11 Note:2,3,4,5,9,13 Note:2,3,4,5,7,9,10 Note:2,3,4,5,8,9,11 Refer to Fig. 4. Note:12 Refer to Fig. 4. Note:12 User adjustable User adjustable User adjustable User adjustable TOE=VDD
--+1 883 ---3.5 -18.5 --5 0.5 -20 -20 -----3.5759 --40 --
----10 10
1.5%2Hz
-40 7.75 --------
dBm mVRMS dBm mVRMS dB dB
Valid Input Signal Levels (each tone of composite signal)
----------tDP tDA tREC tREC tID tDO tPQ
Positive Twist Accept Negative Twist Accept Frequency Deviation Accept Limit Frequency Deviation Reject Limit Thrid Tone Tolerance Noise Tolerance Dial Tone Tolerance
--12 +18 14 4 ----8 12 4.5 50 300 3.5759 --50 --
dB dB dB ms ms ms ms ms ms s s s ns ns MHz ns ns % pf
-16 8.5 40 -40 -11 ----3.581 110 110 60 30
TIMING
Tone Present Detection Time Tone Absent Detection Time Tone Duration Accept Tone Duration Reject Interdigit Pause Accept Interdigit Pause Reject
OUTPUTS
Propagation Delay (St to Q) Propagation Delay (St to StD) Output Data Set Up (Q to Std) Propagation Delay (TOE to Q Enable) Propagation Delay (TOE to Q Disable) tPSED TOE=VDD tQSED TOE=VDD tPTE tPTD fC RL=10k, CL=50pf RL=10k, CL=50pf --
CLOCK
Crystal/Clock Frequency Clock Input Rise Time Clock Input Fall Time Clock Input Duty Time Capacitive Load (OSCO) tLHCL Ext. clock tHLCL Ext. clock DCCL Ext. clock CLO --
Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600 Ohm load. 2. Digit sequences consists of all 16 DTMF tones.
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3. Tone duration = 40mS Tone pause = 40mS. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. Tone pair is deviated by 1.5% 2Hz. 7. Bandwidth limited (3kHz) Gaussian Noise. 8. The precise dial tone frequencies are (350Hz and 440Hz) 2%. 9. For an error rate of less than 1 in 10,000. 10. Referenced to the lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept. 12. For guard time calculation purpose.
SC9270C/D
13. Referenced to Fig.10 Input DTMF Tone level at -25dBm(-28dBm at GS Pin) interference Frequency Range between 480--3400Hz.
5V
SC9270C
1
IN+ INGS VREF IC IC OSCI OSCO VSS VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
0.1f 100nf
5V
SC9270D
1
IN+ INGS VREF INH PWDN OSCI OSCO VSS VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
0.1f 100nf
18 17 16 15 14 13 12 11 10
3.58MHz
300k
100nf 100k 100k
18 17 16 15 14 13 12 11 10
300k
2 3 4 5 6
3.58MHz
100nf Vin 100k 100k 5V
2 3 4 5 6 7 8 9
7 8 9
Figure 2. Single ended input cofiguration
Figure 3. Single ended input cofiguration
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PIN DESCRIPTION
Pin No.
1 2 3
SC9270C/D
Description
Pin Name
IN+ INGS
I/O
I I -Non-Inverting input Inverting input
Connections to the front-end differential amplifier.
Gain select. Gives access to output of front-end differential amplifier for connection of feedback resistor. Reference voltage output, nominally VDD/2. May be used to bias the inputs at mid-rail (see application diagram). Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor. (SC9270D only). (For SC9270C, this pin must be tied to VSS ) Power down (input). Active high power down the device and inhibit the oscillator
4
VREF
O
5
INH
I
6
PWDN
I
internal built-in pull down resistor. (SC9270D only). (For SC9270C, this pin must be tied to VSS )
7 8 9 10
OSC1 OSC2 VSS TOE
I O -I
Clock Input Clock Output
3.579545MHz crystal connected between these pins completes internal oscillator.
Negative power supply, normally connected to 0V. 3-state data output enable. Logic high enables the outputs Q1-Q4. This pin is Internally pulled up. 3-state data outputs. When enabled by TOE, provide the code corresponding to
11~14
Q1 ~ Q4
O
the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. Delayed steering output. Presents a logic high when a received tone-pair has
15
StD
O
been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early steering output. Presents a logic high immediately when the digital
16
ESt
O
algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St causes the device to register the detected tone-pair and update
17
St/GT
I/O
the output latch. A voltage less than VTSt frees the device to accept a new tonepair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St.
18
VDD
--
Positive power supply.
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TIMING DIAGRAM
D A B tREC TONE # n tDP ESt tDA
SC9270C/D
C
tID TONE # n+1 E tDO F G TONE DROPOUT TONE # n+1
EVENTS
tREC
Vin
tGTP
tGTA VTst tPQ
St/GT DATA OUTPUTS Q1 ~ Q4 HIGH IMPEDANCE
DECODED TONE # n -1 tPSTD
DECODED TONE#n
DECODED TONE # n+1
StD OUTPUT TOE tPTE tPTD
Figure 4. Timing diagram
EXPLANATION OF EVENTS
A. Short tone bursts: detected. Tone duration is invalid. B. Tone #n is detected. Tone duration is valid. Decoded to outputs. C. End of tone #n is detected and validated. D. 3 State outputs disabled (high impedance). E. Tone #n + 1 is detected. Tone duration is valid. Decoded to outputs. F. Tristate outputs are enabled. Acceptable drop out of tone #n + 1 does not negister at outputs. G. End of tone #n + 1 is detected and validated.
EXPLANATIONN OF SYMBOLS
Vin: DTMF composite input signal.
tREC
:Maximum DTMF signal duration not detected as valid.
tREC: Minimum DTMF Signal duration required for valid recognition. tID: Minimum time between valid DTMF signals. tDO: Maximum allowable dropout during valid DTMF signal tDP: Time to detect the presence of valid DTMF signals. tDP: Time to detect the absence of valid DTMF signals. tGTP: Guard Time, Tone present. tGTP: Guard Time, Tone absent.
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FUNCTION DESCRIPTIONS
SC9270C/D
The SC9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus.
1. FILTER SECTION
Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond to the bands enclosing the low-group and high-group tones (see table 1). The filter section also in corporates notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order switchedcapacitor section which smooth the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones.
Flow
697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 --
Fhigh
1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 --
KEY
1 2 3 4 5 6 7 8 9 0 * # A B C D ANY
TOE
H H H H H H H H H H H H H H H H L
Q4
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Z
Q3
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Z
Q2
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Z
Q1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE Table 1: Function decode table
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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0
SC9270C/D
PRECISE DIAL TONES X=350Hz Y=440Hz DTMF TONES A=697Hz B=770Hz C=852Hz D=941Hz E=1209Hz F=1336Hz G=1477Hz H=1633Hz
10
20 FREQUENCY (dB) 30
40
50 1kHz X Y AB C D E F G H
FREQUENCY
Figure 5. Filter Response
2. DECODER SECTION
The decoder used digital counting techniques to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm(protects) against tone simulation by extraneous signals, such as voice, while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to "talk-off" and tolerance to the presence of interfering signals ("third tones") and noise. When the detector recognizes the simultaneous presence of two valid tones (referred to as "signal condition" in some industry specifications), it raises the "early steering" flag (ESt). Any subsequent loss of signal condition will cause ESt to fall.
3. STEERING CIRCUIT
Before registration of a decoded tone-pair, the receiver
VDD
checks for a valid signal duration (referred to as "character- recognition-condition"). This check is performed by an external RC time-constant driven by ESt. A logic high on ESt causes VC (see Fig.4) to rise as the capacitor discharges. Provided signal-condition is maintained (ESt remains high) for the validation period (tGTP), Vc reaches the threshold (VTSt) of the steering logic to register the tone-pair, latching its corresponding 4-bit code (see Fig.3) into the output latch. At this point, the GT output is activated and drives VC to VDD. GT
VDD St/GT ESt
0.1f VDD ) VTST VDD ) VDD-VTST
tGTA=(RC)ln( VC
tGTA=(RC)ln(
R StD
Figure 6. Basic steering Circuit
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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SC9270C/D
continues to drive high as long as ESt remains high. Finally after a short delay to allow the output latch to settle, the "delayed-steering" output flag, StD, goes high, signaling that a received tone-pair has been registered.The contents of the output latch are made available on the 4-bit output bus by raising the 3-state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions ("drop-out") too short to be considered a valid pause. The facility, together with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
4. GUARD TIME ADJUSTMENT
In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig.6 is applicable. Component values are chosen according to the following formulae: tREC = tDP + tGTP tID = tDA + tGTA
The value of tDP is a parameter of the device (see table) and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1F is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (tGTP ) and tone-absent (tGTA ). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop - outs would be required. Design information for guard-time adjustment is shown in Fig.7.
VDD C St/GT R1 ESt tGTP=(Rp C)ln( tGTA=(R1 C)ln( Rp= R1R2 R1+R2 VDD ) VDD-VTST VDD VTST ) R2
VDD C St/GT R1 ESt tGTP=(Rp C)ln( tGTA=(R1 C)ln( Rp= R1R2 R1+R2 VDD ) VDD-VTST VDD VTST ) R2
a) Decreasing tGTP (tGTP < tGTA)
b) Decreasing tGTP (tGTP > tGTA)
Figure 7. Guard time adjustment
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5. INPUT CONFIGURATION
SC9270C/D
The input arrangement of the SC9270C/D provides a differential-input operational amplifier as well as a bias source (VREF ) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a singleended configuration, the input pins are connected as shown in Fig.2 with the op-amp connected for unity gain and VREF biasing the input at 1/2VDD. Fig.8 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5.
C1
R1
IN+ + -
SC9270C/D
DIFFERENTIAL INPUT AMPLIFIER
C1=C2=10nF R1=R4=R5=100k R2=60k, R3=37.5k R2*R5 R3= R2+R5 All resistors are +/- 1% tolerance All capacitors are +/- 5% tolerance
C2
R4 R5
INGS
VOLTAGE GAIN (Av diff)=
R3 R2 VREF
R5 R1 R1 +
2
INPUT IMPEDANCE(Zi diff)=2
1 C
2
Figure 8. Differential input configuration
6. POWER - DOWN AND INHIBIT MODE
A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output code will remain the same as the previous detected code (see table 2). fLOW Fhigh 697 1209 697 1336 697 1477 770 1209 770 1336 770 1477 852 1209 852 1336 852 1477 941 1336 941 1209 941 1477 697 1633 770 1633 852 1633 941 1633 --KEY 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY
TOE Q4 Q3 Q2
H H H H H H H H H H H H H H H H L
L L L L L L L H H H H H H H H L Z
L L L H H H H L L L L H H H H L Z
INH = VSS
fLOW Q1 L H 697 H L 697 H H 697 L L 770 L H 770 H L 770 H H 852 L L 852 L H 852 H L 941 H H 941 L L 941 L H 697 H L 770 H H 852 L L 941 Z Z -Table 2: Truth table (Z: high impedance)
Fhigh 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 --
KEY TOE 1 H 2 H 3 H 4 H 5 H 6 H 7 H 8 H 9 H 0 H * H # H A H B H C H D H ANY L
Q4
Q3
Q2
Q1
L L L L L L L H H H H H
L L L H H H H L L L L H
L H H L L H H L L H H L
H L H L H L H L H L H L
PREVIOUS DATA Z Z Z Z
INH = VDD
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6. CRYSTAL OSCILLATOR
The internal clock circuit is completed with the addition of an external 3.579545MHz crystal and is normally connected as shown in Figure 2. However, it is possible to configure several SC9270C/D devices employing only a single oscillator crystal. The oscillator output of the first device in the chain is coupled through a 30pF capacitor to the oscillator input (OSCI) of the next device. Subsequent devices are connected in a similar fashion. Refer to Figure 9 for details. The problems associated with unbalanced loading are not a concern with the arrangement shown, ie: precision balancing capacitors are not required.
SC9270C/D
To OSCI of next SC9270C/D C X-tal OSCI OSCO C
OSCO OSCI
c=30pF X-tal=3.579545MHz
Figure 9 Oscillator Connection
PACKAGE OUTLINE
DIP-18-300-2.54
2.54
UNIT: mm
6.40
1.50 22.95
7.62
15 degree
3.51
0.46
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Rev: 1.1 2001.04.27
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3.30
5.08
0.25

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